VISENGI's SHA-2 Secure Hash Algorithm IP core has been developed to be the highest throughput SHA-2 cryptographic hasher while at the same time making it lightweight and easy to use. The main features of this IP core are:

  • NIST FIPS PUB180-4 Secure Hash Standard compliant SHA-2 implementation
  • Compatible HMAC for Hash Message Authentication as per FIPS PUB 198
  • Fully verified with NIST test vectors
  • Constant hashing input data throughput only dependent on clock frequency:
  • 8'0 bits/sec/Hz for: SHA-224 and SHA-256
  • 12'8 bits/sec/Hz for all others: SHA-384, SHA-512, SHA-512/224, SHA-512/256
  • Achieves >200 MHz on most FPGAs: >1600 Mbps SHA-224,256, and >2560 Mbps for all others
  • Light-weight resource usage with full capabilities:
  • SHA-224,256: under 2K Registers and LUT6s (no BRAM or DSPs needed)
  • SHA-384,512,512/*: under 3K5 Registers and LUT6s (no BRAM or DSPs needed)
  • Industry standard AXI4-Stream (AXI4-ST) I/O interfaces
  • Zero-configuration: Fully data-driven control (i.e. message boundaries from data stream)
  • I/O data width for full throughput: 32 bits for SHA-224/256, 64 bits for all others
  • Arbitrary bit length inputs supported (except 0 bits)
  • Unlimited message sizes (up to 2 to the 64 or 128 bits, as per standard)
  • No start latency and minimal hash end latency (<172 clock cycles per hash operation)
  • Further reduced sizes available: when padding is not necessary or input is word/byte aligned

Quotation Request


The interfaces use the very simple AXI4-Stream (aka AXI4-ST) industry standard bus, FIFO like, for input data and output hash. Included with the IP core source code is a testbench with NIST's test vectors, it is easily modifiable to feed any other data source in simulation.

Upon request there is also the possibility of custom I/O interfaces' variations (i.e. AXI3/4 DMA memory mapped input data, AXI-Lite slave for hash output, etc).


Constant Input Data Hashing Throughput for each SHA2 mode:

SHA-2 Mode Output Hash bit size Raw Hash Throughput Hash Throughput @100 MHz Hash Throughput @200 MHz
SHA-224 224 8 bits/sec/Hz 800 Mbps 1600 Mbps
SHA-256 256 8 bits/sec/Hz 800 Mbps 1600 Mbps
SHA-512/224 224 12'8 bits/sec/Hz 1280 Mbps 2560 Mbps
SHA-512/256 256 12'8 bits/sec/Hz 1280 Mbps 2560 Mbps
SHA-384 384 12'8 bits/sec/Hz 1280 Mbps 2560 Mbps
SHA-512 512 12'8 bits/sec/Hz 1280 Mbps 2560 Mbps


Included with the core is:

Quotation Request

  • IP Core Datasheet
  • Xilinx Vivado Block Design drag'n'drop instance
  • Intel Quartus Qsys/Platform Designer drag'n'drop instance
  • Instantiation Template
  • Technical support via email
  • Complete Testbench for source code

For any further information on this core or if you would like to receive a price quotation, please use the Contact form or the Quote Request button.