PNG Encoder

Features

 

 

         VISENGI's PNG Encoder IP core has been developed to be a standards compliant high speed hardware lossless PNG image compressor. Its main features are:
 
  • PNG compression standard ISO/IEC 15948:2003
  • ZLIB and Deflate implementations as per RFC1950 and RFC1951
  • Standard headers and special mode for headerless operation
  • Lossless 24 bits True Color and 8/16 bits grayscale pixels encoding
  • Fast fixed Huffman coupled with efficient deflate algorithm
  • Parameterizable ratio of compression efficiency vs. IP core size
  • Simple FIFO like I/O interfaces
  • Constant Realtime throughput: 1 pixel compressed per clock cycle
  • Small start and end latencies, plus one cycle between lines
 
 
     The compression ratio attained varies greatly depending on the type of image being processed. For example PC screenshots, maps, and graphs compress extremely well under PNG, as opposed to photos and scanned sources. Actually, PNG is complementary to the JPEG standard, which has the opposite behavior.
 
 
 

Quotation Request

You may also be interested in VISENGI's PNG Decoder IP Core...
 
 
 

 

Interfaces

 
    The data interfaces used by the PNG Encoder IP Core (PNGE) are simple FIFO like interfaces with a minimal control/status bus. This is due to the lossless nature of PNG, which actually does not need any parameters.
 
The input/output interfaces of the PNGE IP core is divided in three different parts:
 
  • Control/Status Interface: control bits to perform soft-reset, to select encoding with PNG headers or headerless, indicate image dimensions and a single status bit to know when PNGE is ready or busy.
 
  • Input Interface: used to feed the core with pixels to compress. It is a very simple FIFO interface that requests pixels row-wise (from left to right and top to bottom).
 
  • Output Interface: simple sequential output of the PNG image's bytes. In the form of a 32 bits FIFO interface with byte enables.
 

 

Resource Usage

     In the next table you can find the synthesis results for each FPGA type (Xilinx and Altera) in which the core may be fitted. Please note that if your exact FPGA can not be found but it has enough resources compared to another FPGA of the same family, then it is also supported. If you are looking for synthesis results for other FPGA vendors or for ASIC targets, please contact us with your specific needs.

 

Vendor Family Device Logic Usage BRAMs MULTs/DSPs Max. Freq.
Vendor Family Device Logic Usage BRAMs MULTs/DSPs Max. Freq.

 

 

Support

Included with the core is:

Quotation Request

 

• Technical support up to successful integration

• IP Core Datasheet

• Complete Testbench

• PNG SW analysis tools and guidance

 

 

For any further information on this core or if you would like to receive a price quotation, please use the contact form or the Quote Request button.