VISENGI's H.264 Decoder IP core has been developed to match exclusively the profiles of VISENGI's H.264 Encoder IP core, which itself implements a subset of the High 4:4:4 Predictive Profile of the H.264 specification. VISENGI offers two decoder variants to meet the different versions of the encoder it targets:

- H264D-I: H.264 decoder compliant with the subset of CAVLC 4:4:4 Intra Profile (all frames are keyframes) used by VISENGI's H.264 Encoder IP core version H264E-I.
- H264D-P: H.264 decoder compliant with the subset of High 4:4:4 Predictive Profile used by VISENGI's H.264 Encoder IP core version H264E-P. Plus the H264D-PME with Motion Compensation to match H264E-P WME.

Note that this is not a universal H.264 Decoder, but one tailored to the subset of the standard employed by VISENGI's H.264 Encoder IP core. Thanks to this, the huge throughput and lowest latency of the Encoder IP core can also be matched by this H.264 Decoder IP core

Quotation Request

  • Video compression standard ITU.T Rec. H.264 | ISO/IEC 14496-10 AVC.

  • Follows H.264 standard's Annex B byte stream format.

  • Multiple stream decoding capability fully in parallel.

  • Scalable architecture, to strike the right balance of size and latency vs. pixel throughput.

  • Up to 8 frame buffers per stream and up to 32 input data buffers.

  • Very low latency from first data input to pixel output.

  • High 4:4:4 Predictive Profile (H264D-P) and CAVLC 4:4:4 Intra Profile (H264D-I and H264D-P) matching VISENGI's H.264 Encoders.

  • Motion Compensation capability (H264D-PME)

  • Preserves full color fidelity with color subsampling 4:4:4.

  • Industry standard interfaces: AXI-Lite slave for configuration/status and AXI3/4 master for coded-input/pixel-output.

  • Embedded DMA engines in AXI3/4 interfaces for direct connection to a memory controller. Support for high latency memories.

  • Add-on module for AXI4-ST streaming video output of decoded pixels in row-wise order.

You may also be interested in VISENGI's H.264 Encoder IP Core...


The data interfaces in the H.264 Decoder IP Core (H264D) use the AXI industry standard. The Master I/O data interfaces use an AXI3 bus, forward compatible with AXI4 interconnects.

The input/output interfaces of the H264E IP core are the following:

  • Configuration Interface: AXI-Lite slave with a 32 bits data interface

  • Data I/O Interface: AXI3/4 Master read-only interface with a data width of 32 bits for reading input H.264 coded files from memory.

  • Pixel Interface: AXI3/4 Master interface with a data width of 128 bits used for writing decoded frames to memory and (only for H264D-P) reading decoded frames as reference frames.

  • Motion Compensation Interface (only for H264D-PME): Optional AXI3/4 Master read-only interface with a data width of 256 bits, used for reading decoded frames to memory exclusively for motion compensation.

  • Interrupt output: Rising-edge interrupt, user programmable, to signal events such as stream corruption, frame decoded, etc.

One clock and one reset port are shared for all interfaces. The IP core allows address widths of up to 44 bits, by default all address ports are set to 32 bits wide. These are byte-addressable, as per the AXI specification.


Included with the core is: Quotation Request

  • Technical support via email
  • IP Core Datasheet
  • Xilinx Vivado drag'n'drop instance
  • Intel Quartus drag'n'drop instance
  • Linux driver for embedded setups
  • Example SW control application

For any further information on this core or if you would like to receive a price quotation, please use the Contact form or the Quote Request button.