VISENGI's Advanced Encryption Standard (AES) IP core provides AES-128, AES-192, and AES-256 encryption and decryption, as per FIPS-197, with a shockingly small resource usage, while allowing a large operating frequency.
The IP core's main features are:

  • AES algorithm following Federal Information Processing Standards 197 (FIPS PUB 197).

  • Constant encryption/decryption throughput, depending only on key size:

    • AES128 (128 bits key): 77 cycles per 128 bits of data (1.66 Mbps/MHz)
    • AES192 (192 bits key): 91 cycles per 128 bits of data (1.40 Mbps/MHz)
    • AES256 (256 bits key): 105 cycles per 128 bits of data (1.21 Mbps/MHz)
  • Low latency one-time key expansion (<100 cycles) on all modes' start-up.

  • ECB block cipher mode of operation, quick adaptability to any mode (CBC, CTR, …).

  • Extremely simple FIFO-like 32 bits wide I/O.

  • Automatic key-length (AES128/AES192/AES256) inference.

The data interfaces used are simple FIFO-like with minimal control bits. The key size (AES128/192/256) is automatically inferred from the number of 32 bits words input when a new key is supplied (4, 6, or 8 cycles).

The input/output interfaces of the AES IP core are divided in three different parts: Quotation Request

  • Control Interface: control bit to indicate encryption or decryption.

  • Input Interface: shared 32 bits bus for both supplying a key and user data to encrypt/decrypt. It is a simple FIFO interface with a ready output and a data valid input.

  • Output Interface: simple 32 bits sequential output of the encrypted/decrypted data.

For user-connection's convenience this IP core is designed with 32 bits wide buses. Hence, the AES' native blocks of 128 bits are input as 4 words of 32 bits one after the other, without pauses in between. The same is expected for the keys of size 128 bits (4 contiguous words of 32 bits), 192 bits (6 words), and 256 bits (8 words).

Resource Usage

In the next table you can find the synthesis results several FPGA vendors and families in which the core may be fitted. Please note that if your exact FPGA can not be found but it has enough resources compared to another FPGA, then it will doubtlessly also fit. In any case, if you would like to know the precise synthesis results for your specific FPGA or for ASIC targets, please contact us with your specific target.

VendorFamilySpeedRegsLUTsBlockRAMsMax. Freq.Throughput
VendorFamilySpeedRegsLUTsBlockRAMsMax. Freq.Throughput
XilinxVirtex-6-158510751314 MHz521 Mbps
XilinxVirtex-5-158810571271 MHz450 Mbps
XilinxVirtex-4-1268420921262 MHz435 Mbps
XilinxZynq-158510631300 MHz498 Mbps
XilinxZynq-358510591414 MHz688 Mbps
XilinxArtix-7-158611121252 MHz418 Mbps
XilinxArtix-7-358511131346 MHz575 Mbps
XilinxKintex-7-158510611335 MHz556 Mbps
XilinxKintex-7-358510661454 MHz754 Mbps
XilinxSpartan-6-259211171167 MHz277 Mbps
XilinxSpartan-6-359011171192 MHz319 Mbps
XilinxSpartan-3A DSP-459321761139 MHz231 Mbps
XilinxSpartan-3A DSP-559521741171 MHz284 Mbps
XilinxSpartan-3A-459321761139 MHz231 Mbps
XilinxSpartan-3A-559521741171 MHz284 Mbps
AlteraCyclone IIIC771323072048 bits182 MHz302 Mbps
AlteraCyclone IVC671323072048 bits189 MHz314 Mbps
AlteraCyclone VC67545952048 bits262 MHz435 Mbps
AlteraArria II GXI37147972048 bits260 MHz432 Mbps

Methodology notes:

  • Synthesis results were obtained using the freely available versions of Xilinx ISE and Altera Quartus environments, with speed optimization efforts set to high.

  • Maximum frequency is that reported by Synthesis for Xilinx ISE, and TimeQuest's Slowest V/T model for Altera Quartus.

  • Maximum throughput refers to AES128 and is calculated as: Max. frequency x 128 bits per block / 77 cycles per block.


Included with the core is:

Quotation Request

  • Technical support via email
  • IP Core Datasheet
  • Instantiation Template
  • Complete Testbench for source code

For any further information on this core or if you would like to receive a price quotation, please use the Contact form or the Quote Request button.