ZBT SRAM Controller

Features

 

This hardware IP core is a ZBT SRAM controller capable of automatically managing single address and full continuous burst read/writes to ZBT SRAM memory chips.

  • Customizable to any ZBT SRAM memory chip combination.
  • Customizable to any FPGA bus (Wishbone, AMBA, OPB, etc.).
  • Continuous burst reads/writes.
  • Single cycle reads/writes.
  • Individual byte enables.

 

Typical burst access waveform from a Wishbone bus device: 

 

  

 

Support

Included with the core is:

Quotation Request

 

• Full technical support up to successful client integration

• Documentation and design examples

• Complete Testbench

• Synthesis scripts and results

• Instantation Template

 

For any further information on this core or if you would like to receive a price quotation, please use the contact form or the Quote Request button.