PNG Decoder

Features

 

 

              VISENGI's PNG Decoder IP core has been developed to be a standards compliant high speed hardware lossless PNG image decompressor. Its main features are:
 
  • PNG compression standard ISO/IEC 15948:2003
  • ZLIB and Deflate implementations as per RFC1950 and RFC1951
  • Standard headers and special mode for headerless operation
  • Simple FIFO like I/O interfaces
  • Worst case throughput: 0.5 pixels decoded per clock cycle
  • Best case throughput: 1 pixels decoded per clock cycle
  • Small processing latency at start and end of decoding
  • Built-in PNG stream error checking
 
 
Type of PNG files supported:
 
  • True Color 24 bits pixels (8 bits per sample)
  • PNGs encoded with fixed Huffman blocks or uncompressed blocks (no dynamic Huffman)
  • Optional headers are automatically bypassed
 
      Well compressed PNG files will decode at a throughput closer to 1 decoded pixel per cycle, while the less compressed ones (closer to 1:1 compression ratio) will see the throughput closer 1 decoded pixel per 2 cycles.
 
 

Quotation Request

 
You may also be interested in VISENGI's PNG Encoder IP Core...
 
 
 

Interfaces

 
    The data interfaces used by the PNG Decoder IP Core (PNGD) are simple FIFO like interfaces with a minimal control/status bus. This is due to the lossless nature of PNG, which actually does not need any parameters.
 
The input/output interfaces of the PNGD IP core are divided in three different parts:
 
  • Control/Status Interface: control bits to perform soft-reset, to select decoding with PNG headers or headerless, indicate image dimensions in case of headerless decoding, and a status bits to know when PNGD is ready or busy, decoded image dimensions (if PNG headers are present), and an error status output to indicate when an error is detected in the PNG stream.
 
  • Input Interface: used to feed the core with data to decompress. It features a FIFO interface that sequentially requests a PNG file's bytes in the form of 32 bits words (with corresponding byte enables).
 
  • Output Interface: simple FIFO interface that outputs decoded pixels row-wise (from left to right and top to bottom)

 

 

Resource Usage

     In the next table you can find the synthesis results for each FPGA type (Xilinx and Altera) in which the core may be fitted. Please note that if your exact FPGA can not be found but it has enough resources compared to another FPGA of the same family, then it is also supported. If you are looking for synthesis results for other FPGA vendors or for ASIC targets, please contact us with your specific needs.

 

Vendor Family Device Logic Usage BRAMs MULTs/DSPs Max. Freq.
Vendor Family Device Logic Usage BRAMs MULTs/DSPs Max. Freq.

 

 

Support

Included with the core is:

Quotation Request

 

• Technical support up to successful integration

• IP Core Datasheet

• Complete Testbench

• PNG SW analysis tools and guidance

 

 

For any further information on this core or if you would like to receive a price quotation, please use the contact form or the Quote Request button.