Features

     VISENGI's JPEG Decoder IP core has been developed to be a complete standards compliant JPEG / MJPEG Hardware Decompressor / Decoder. Its main features are:

• Baseline DCT decoder according to JPEG ITU-T T.81 | ISO/IEC 10918-1 standard

• Seamless Motion JPEG (MJPEG) decoding
• Dual pixel output to reach top speed (4 pixels decoded every 3 cycles)
• Maximum number of Huffman and Quantization tables allowed by specification (four each)
• Selectable maximum number of color components
• Unlimited chroma subsamplings, grayscale and multi-scan JPEGs
• Unlimited image size (specification up to 64K x64K)
• Allows RST (restart intervals) and DNL (for multi-scan images) markers
• Selectable YCbCr and/or RGB output
• Throughput: up to 4 pixels output every 3 clock cycles

Throughput

     In decoding JPEG images, pixel throughput can not be fixed or constant for compressed JPEGs of any quality, as it depends on the compression ratio (bits needed to encode one pixel).

    To circumvent this limitation VISENGI's JPEG Decoder features a dual pixel component pipeline, allowing for greater decoding speeds. And what is more important, a highly optimized Huffman decoder has been designed and fine tuned into the system. These two features coupled make our JPEG Decoder unique in guaranteeing decoding speed even for the highest quality images (worst compression ratios), while other decoders can only sustain their throughputs at lower qualities.

 (*) Minimum compression ratio to guarantee the fixed decoding speed indicated in the "Pixels / Cycle" column 

(**) Approximate maximum Quality ratio where minimum compression ratio is reached (see JPEG Encoder for image quality assessment)

     Please note the table exemplifies four very common chroma subsamplings, although the JPEG Decoder IP Core is NOT limited to these subsamplings.

Resource Usage

     In the next table you can find the synthesis results for each FPGA type (Xilinx, Altera, and Actel) in which the core may be fitted. Please note that if your exact FPGA can not be found but it has enough resources compared to another FPGA of the same family, then it is also supported (especially in the Actel case, where logic usage is in Core Cells). If you are looking for synthesis results for other FPGA vendors or for ASIC targets, please contact us with your specific needs.

Support

Included with the core is:

• Full technical support up to successful client integration

• Documentation and design examples

• Complete Testbench

• Synthesis scripts and results

• Instantation Template

For any further information on this core or if you would like to receive a price quotation, please use the contact form or the Quote Request button.