Frequently Asked Questions

 

 

 

If you have any other question about our products or services, please do not hesitate to contact us. You can do so through the contact form or directing an email to the appropriate department in the Contact section.

 

 

 


Q: What kind of technical support do you offer?

We are proud to offer our clients a top-notch technical support. As such, the client will be able to count on our engineers to work side by side with his team in the development process, up to the successful integration of VISENGI's IP cores into the final system. It is only at this point that we feel our objective to be accomplished.


Q: How are your cores licensed?

 VISENGI's cores are licensed on four categories, to best suit the client's needs and leverage the cost:

  • License for a single project:
    • Netlist format (valid for only one type of FPGA)
    • RTL format (valid for any FPGA/ASIC)
  • License for unlimited projects:
    • Netlist format (valid for only one type of FPGA)
    • RTL format (valid for any FPGA/ASIC)


Q: What does Netlist format mean?

A Netlist is a precompiled and technology/vendor dependent form of IP core delivery for use in FPGA targets. When a client chooses this format, the intended FPGA's complete part name is sent to us and a Netlist is generated with the appropriate tool. The client will receive this Netlist file along with the documentation and full implementation guidelines to use it.

The downside of this format is that it can be synthesized only for one type of FPGA device. Retargeting it to another device will imply an extra fee.


Q: What does RTL format mean?

RTL format is a fully synthesizable VHDL code in an unreadable form. Strictly speaking it could be considered an obfuscated source code. This is done to protect VISENGI's intellectual property while still letting the licensee use the core without restrictions in any FPGA or ASIC. 


Q: Are there any royalty fees associated with the use of your cores?

We license our cores on a one time fee basis, independent of your intended use or production volume.


Q: Are there any restrictions when licensing an IP core?

An obvious restriction that applies and is common to the IP industry is that the licensee may not resell the IP core itself unless as part of another system. This license model is really very open and convenient for both parts.

If you have any questions about the license or how it would apply in your specific situation, please do not hesitate to contact us.


Q: What Hardware description language (HDL) is used in the source code?

At VISENGI we base our developments in the VHDL language, defined in IEEE standard 1076, which lets us implement our solutions at the lowest level while meeting the strictest time to market requirements.


Q: Do I have to generate any internal cores (RAM, FIFO, etc.) to be able to synthesize an IP core?

No. Any needed RAMs, ROMs, FIFOs, etc. are supplied as inferable cores in the form of VHDL files. This is the most convenient format, as it assures the most efficient implementation and best usability (it is vendor independent) than any pregenerated core form.